With continuous development of semiconductor processing technology, semiconductor technology node follows development trend of Moore's Law and continues to shrink. In order to adapt to the shrinking process node, channel length of metal-oxide-semiconductor field effect transistor (MOSFET) needs to be continuously reduced. Reducing the channel length has advantages such as increasing chip (or die) density and increasing switching speed of the MOSFET.
However, with the reducing of the channel length of a device, the distance between source and drain of the device is also reduced accordingly. Thus, the ability of a gate to control the channel becomes lower. It becomes more difficult for gate voltage to pinch off the channel. As a result, a subthreshold leakage phenomenon, i.e., short-channel effects (SCE) can occur more easily.
Therefore, in order to better adapt to requirements of scaling down the size of the device, semiconductor processes have started to gradually transition from planar MOSFET to three-dimensional type transistor that has greater functionality, such as fin field effect transistor (FinFET). The gate of a FinFET can control an ultra-thin body (fin) at least from both sides, and thus can have a much greater ability to control the channel than the gate in a planar MOSFET device. Therefore, the gate of the FinFET can well suppress the SCE. In addition, in comparison with other devices, the FinFET can have better compatibility with existing integrated circuit manufacturing technology.
However, to meet the development trend of Moore's Law, the fin of a FinFET is required to have a smaller width (i.e. fin width). A fin width formed by etching a semiconductor substrate using a conventional mask as an etch mask can no longer meet the requirement. The disclosed methods and devices are directed to solve one or more problems set forth above and other problems.